On September 2, 2026, the Federal Circuit issued three opinions in Netlist, Inc. v. Micron Technology, Inc., all affirming PTAB final written decisions that Netlist memory claims are unpatentable as obvious. The panel in each case was Reyna, Linn, and Stark. Samsung Electronics originally petitioned. Micron filed parallel petitions, was joined or consolidated, and remained after Samsung settled with Netlist and withdrew. These appeals are from IPRs. They are not the DDR5-module patents on the existing C.D. Cal. / ITC 3930 Netlist-Micron card.

The precedential opinion: DIMM buffers

No. 2024-1707 (Reyna, J.) reviews IPR2022-00639 and IPR2023-00204 on U.S. Patent 10,949,339, claims 1-35. The patent is directed to dual in-line memory modules that insert buffers between a memory controller and DRAM, with data paths ordinarily disabled and selectively enabled during reads and writes. The Board found all challenged claims obvious over U.S. Patent Application Publication 2006/0277355 (Ellsberry) and/or U.S. Patent 7,024,518 (Halbert). The court held that substantial evidence supports the Board on the disputed "latency parameter" and "enable data path" limitations of representative claim 1. Any error in discussing Netlist's own U.S. Patent 7,532,537, which was not part of Samsung's petition ground, was harmless because the Board also found Ellsberry alone teaches adding a clock cycle for propagation delay. AFFIRMED. Costs against Netlist.

On-module voltage converters

Nos. 2024-1859 and 2024-1863 (Linn, J., nonprecedential) review four IPRs on U.S. Patents 11,016,918 and 11,232,054, claims 1-30 of each. The patents describe DIMMs with on-module voltage converters that take host power and generate regulated voltages for devices on the module. The Board found the claims obvious over U.S. Patent Publication 2006/0174140 (Harris) and the JEDEC Fully Buffered DIMM standards, with U.S. Patents 7,724,604 (Amidi) and 6,856,556 (Hajeck) added for certain monitoring/anomaly dependents. The court rejected Netlist's petition-scope and teaching-away attacks on the Harris-FBDIMM combination for power through edge connectors. AFFIRMED.

3DS packages and TSV load

Nos. 2024-2240 and 2024-2241 (Stark, J., nonprecedential) review four IPRs holding unpatentable all claims of U.S. Patents 8,787,060 and 9,318,160. The patents share a specification and concern three-dimensional stack memory packages. They purport to reduce driver load by how array dies connect to a control die, including through-silicon vias. Representative claim 1 of the '060 patent was obvious over Kim (2011/0103156) and Rajan (8,041,881). Claim 7 is not limited to different-length TSVs: load difference can be considered even when that difference is zero. AFFIRMED. The opinion treats 2024-1859 as a related appeal issued the same day.

What it means in practice

A settlement with the original IPR petitioner does not end the appeal if a joined or consolidated petitioner remains. On the merits, the precedential piece is a substantial-evidence affirmance of buffer-timing and data-path findings grounded in JEDEC-compatible prior art, not a new obviousness rule. The two companions are nonprecedential and should be cited that way.

What to watch next

Whether Netlist seeks rehearing or certiorari on the '339 patent, and how the still-live C.D. Cal. case and ITC DN 3930 (different patents) proceed against this PTAB backdrop.